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 Sr. CAD Engineer - Timing for Transistor-Level Flows & Methodologies - Austin, Texas, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200116299 / Latpro-3736560 
Date posted: Apr-21-2020
State, Zip: Texas, 78729

Description

Sr. CAD Engineer - Timing for Transistor-Level Flows & Methodologies

Austin , Texas , United States

Hardware

Summary

Posted: Oct 23, 2019

Role Number: 200116299

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this role you will own defining, implementing, and supporting the methodologies, flows, and tools necessary to verify transistor-level circuits in the areas of timing, signal integrity and circuit verification. You will work very closely with digital and analog designers to ensure that their designs meet functionality, timing, electrical, power, and signal integrity goals.

Key Qualifications

  • Typically requires at least 3+ years of hands on experience in timing, STA, CAD/methodology, etc.
  • Proficiency in STA and methodologies for timing closure, signal integrity analysis, cross-talk, and OCV (AOCV, POCV) effects, etc.
  • Proficiency in formal/functional/logic-to-circuit equivalence checking (FEC) techniques and implementation a plus.
  • Experience with transistor-level tools such as NanoTime, PathMill, ESP (Verilog to Spice equivalence checking), LEC, HSPICE.
  • Familiar with digital custom circuit designs including dynamic circuit techniques and memories as well as SPICE models and netlists.
  • Experience programming in Perl, TCL, or similar language.
  • Strong communicator who can accurately describe issues and follow them through to completion.

Description

As a Sr. CAD Engineer, you will: - Collaborate with design teams to understand and debug tool issues and constraints - Build/maintain flows, scripts and methodologies for transistor level analysis - Work closely with design teams and CAD to drive timing, power, signal integrity, and functional verification closure efforts - Deep analysis of timing paths to identify key issues - Document and help with guidelines/specs

Education & Experience

BS, MS preferred, degree in technical field



Requirements

See job description

 

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