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 Sr. CAD Engineer - Timing for Gate-Level Flows & Methodologies - Austin, Texas, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Networks
Computers - Software Engineer
Computers - Webmaster
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200064433 / Latpro-3738012 
Date posted: Apr-22-2020
State, Zip: Texas, 78729


Sr. CAD Engineer - Timing for Gate-Level Flows & Methodologies

Austin , Texas , United States



Posted: Jul 23, 2019

Role Number: 200064433

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this role, you will be responsible for all aspects of timing including working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure.

Key Qualifications

  • Typically requires 8+ years of hands on experience in static timing analysis flows as well as:
  • Deep knowledge of STA of large high-performance SoC or Processor designs in deep sub-micron technologies
  • Proficiency in analysis, tools, and methodologies for timing closure
  • Deep understanding of noise, cross-talk, OCV effects, margins, and constraints
  • Programming experience in Perl, Python, Tcl, C++ or other languages
  • Strong communicator who can accurately assess, describe issues to management and follow solutions through to completion
  • Familiarity with timing and power ECO techniques and implementation is a positive
  • Familiarity with circuit modeling, including SPICE models and worst-case corner selection is a positive


In this highly visible role, you will: - Collaborate with design teams to understand and debug issues related to constraints, flow scripts, and timing closure - Facilitate and drive STA methodology changes to improve overall STA flows - Create/maintain scripts and methods for timing analysis and power reduction - Deep analysis of timing paths to identify key issues - Implement infrastructure to facilitate data mining and visualization - Help build timing and power ECO custom scripts for project tapeout - Partner with Physical Design team, highlighting issues and standard methodologies - Document and help with guidelines/specs

Education & Experience

BS, MS/PhD* preferred, degree in technical field (*if fewer years of experience)


See job description


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