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 IC Packaging Engineer - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Other
Engineering - Other
Computers - Software Engineer
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200000909 / Latpro-3738512 
Date posted: Apr-22-2020
State, Zip: California, 95014


IC Packaging Engineer

Santa Clara Valley (Cupertino) , California , United States



Posted: Feb 27, 2019

Role Number: 200000909

Do you like to work on groundbreaking technologies that enable amazing new products? Do you have the attention for details and love for excellence to work towards an extraordinary result? We are looking for a talented and passionate IC Packaging Engineer to join our team. In this highly visible role, you will own and drive advanced package selection, new product package structure and configuration optimization. You will be responsible for package/SIP layout, optimization, design verification and taping out.

Key Qualifications

  • Minimum 5+ years hands on experience with Cadence APD/SIP
  • Solid signal and power integrity fundamentals
  • Must have experience in package design, design for manufacturing review.
  • Familiar with layout review tools such as CAM350/Valor or Calibre.
  • 2D/2.5D and 3D package connection, memory package, stacked die substrate design experience.
  • Familiar with BGA package substrate technologies.
  • Experience preferred in schematic capture, layout and design using Cadence Allegro Schematic Design Entry (Concept HDL) design tools is a plus.
  • Exposure to Unix environment, scripting languages (PERL, Python, TCL and/or shell) and methodology is a plus


Interface and coordinate with cross-functional groups throughout Apple on new product package/SIP selection, feasibility analysis and design. Implement the physical design of SIP, SoC and memory chips. Work cross-functionally, understand trade-offs, constraints, and optimizing silicon floor plan, bump and package pin out. To optimize signal/power integrity of package/SIP design. Drive methodology, innovations, and productivity improvements in package design together with vendors and developers on feature development and bug resolution.

Education & Experience

BS or MS Electrical Engineering, Mechanical Engineering, Materials Science or Physics required and relevant experience within technical discipline. PhD is a plus.


See job description


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