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 SoC Physical Design Verification Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
Engineering - Electrical
Engineering - Telecom
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200037112 / Latpro-3738531 
Date posted: Apr-22-2020
State, Zip: California, 95014

Description

SoC Physical Design Verification Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: May 28, 2019

Role Number: 200037112

At Apple, we work every single day to craft products that enrich people's lives. Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices. In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.

Key Qualifications

  • You have 5-10 years of physical design experience, with emphasis on physical verification.
  • Strong knowledge of physical verification flows and methodology.
  • Knowledge of all aspects of ASIC physical design.
  • Scripting skills to debug flow related issues and make enhancements as appropriate.
  • Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
  • Real chip tapeout experience with a track record of successful signoff.
  • Layout design background and experience a plus.

Description

As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level. You'll collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You'll work on padring, bump, RDL design, and working with the package and floorplan teams.

Education & Experience

You have a BSEE or MSEE.



Requirements

See job description

 

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