CAD Engineer - Design Verification Methodology
Santa Clara Valley (Cupertino) , California , United States
Posted: Mar 19, 2020
Role Number: 200000984
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple's silicon designs in software simulation. You will create software which will help design verification engineers find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will influence the design of the next generation of these regression systems. Your insight and skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with issues will be important contributions to an extended CAD team that comprehensively supports Apple's DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve issues. You will also be working on developing solutions for the future that involve using ML and AI.
- We typically require at least 5+ years of experience with MSEE/CE/CS preferred
- Working knowledge of Verilog and/or SystemVerilog
- Knowledge of SQL style databases and query language preferred.
- Strong experience with Synopsys VCS, Incisive/Xcelium, or Modelsim
- Strong programming abilities in Python and/or PERL are required; We consider Java and TCL a plus
- Good communication skills are required and prior user support experience is a plus
- Experience with front end web development and UI is a plus
- Experience with UVM, VMM or OVM a plus
- Familiarity with Verdi, Indago and/or Simvision is considered a plus
- Knowledge of C and C++ preferred
On our team, you will:
Develop, deploy, and support robust, configurable, and scalable tools to enable hardware verification across multiple projects
Identify, gather, and analyze metrics for improved automation reliability and hardware verification performance
Help to debug vendor tool issues
Interact with the DV team to help solve their problems
Education & Experience
MS or BS Degree in a technical discipline.