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 RTL Design Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
Engineering - Electrical
Engineering - Telecom
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200001705 / Latpro-3738633 
Date posted: Apr-22-2020
State, Zip: California, 95014

Description

RTL Design Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Oct 23, 2018

Role Number: 200001705

At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented RTL Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. You will join the DDR PHY design team. We provide best-in-class PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.

Key Qualifications

  • The ideal candidate will have five or more years of experience in logic design with the following qualifications:
  • RTL design using Verilog or SystemVerilog, assertion writing
  • Design of state machines, data paths, arbitration and clock domain crossing logic
  • Logic synthesis, timing constraints
  • Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
  • Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
  • Prior experience in DDR PHY design and mixed-signal environment is a plus

Description

In this role, you will be responsible for: Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs. Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. Providing high-quality RTL description, including assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality. Supporting design verification to insure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance and power characterization.

Education & Experience

Bachelors or Masters Degree in Electrical Engineering or Computer Science



Requirements

See job description

 

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