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 DFT Design Verification Engineer - Austin, Texas, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
Engineering - Electrical
Engineering - Telecom
Computers - Software Engineer
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200001229 / Latpro-3738649 
Date posted: Apr-22-2020
State, Zip: Texas, 78729


DFT Design Verification Engineer

Austin , Texas , United States



Posted: Oct 22, 2018

Role Number: 200001229

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. The DFT Design Verification Engineer will be on a small team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of a GPU core. This person will create and maintain verification test bench components and environments, need to be proficient with scripting and Verilog, as well as be able to come up with test plans and validate IP.

Key Qualifications

  • Experience with Verilog / SystemVerilog
  • Knowledge of IEEE 1500 and IEEE 1149
  • Experience debugging simulation waves.
  • Experience working under strict schedule deadlines with the ability to manage multiple priorities
  • Experience with Perl, Shell scripting, Makefiles, TCL a plus
  • Excellent communication skills and ability to collaborate


We would like you have the following skills and experience: Develop verification plans in coordination with design leads and architects Create and maintain verification test bench components and environments Generate directed and directed random tests in RTL and gatesim environments Analyze coverage, and enhance test environment to target coverage holes Create automated verification flows for block verification Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs

Education & Experience

BS/MS/PhD CE, EE, CS, or related field


See job description


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