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 Analog IP Lab System Characterization Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
Engineering - Electrical
Electronics
Engineering - Telecom
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200139179 / Latpro-3738936 
Date posted: Apr-22-2020
State, Zip: California, 95014

Description

Analog IP Lab System Characterization Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Jan 9, 2020

Role Number: 200139179

In this highly visible role, you will perform lab system interoperability characterization and validation of embedded system circuits; working with many disciplines to launch the world's premiere mobile computing chips. At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and especially hardworking IP Validation Lab Software Developer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will surprise and delight millions of Apple's customers everyday

Key Qualifications

  • The ideal candidate possesses the following qualifications:
  • Experience in interoperability test development, debug, and reporting
  • Excellent test and script programming skills, Python preferred
  • Experience with electronic measurement, protocol analyzers/exerciser equipment
  • Experience in testing serial I/O, SERDES, and memory interfaces

Description

-Protocol level testing, debug, and characterization of chip interfaces -Debug of protocol level interoperability and compliance failures -Setup, debug, and maintain lab system test environment -Develop and execute software scripts to automate stress and coverage tests -Collaborate with chip design teams, system HW and SW design teams

Education & Experience

-BSEE, BS-ECE is required -MSEE, MS-ECE is a plus



Requirements

See job description

 

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