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 PHY Design Verification Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
Engineering - Electrical
Engineering - Telecom
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200122594 / Latpro-3739267 
Date posted: Apr-22-2020
State, Zip: California, 95014

Description

PHY Design Verification Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Nov 15, 2019

Role Number: 200122594

Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a critical impact on getting functional wireless products to hundreds of millions of customers quickly.

Key Qualifications

  • 3+ years of verification experience of wireless/wired communication block/subsystem.
  • Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
  • Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
  • Experience of using Matlab/C reference model and bit-accurate verification a plus.
  • Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.
  • Proficiency in shell and Perl scripting, Python skills a plus.
  • Experience of Palladium/FPGA validation a plus.
  • Should be a team player with excellent communication skills, self-motivated and well organized.

Description

- Work closely with system/design team to review and understand PHY subsystem microarchitecture, create verification plans from specifications. - Build block/subsystem level test benches with reference model, using best in class DV methodology. Architect test benches with maximum reusability in mind. - Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found. - Create and analyze block/subsystem level coverage model, and add test cases to increase coverage. - Support PHY subsystem validation using Palladium and/or FPGA.

Education & Experience

BS required, MSEE preferred

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.





Requirements

See job description

 

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