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 Extraction CAD Engineer - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
Engineering - Electrical
Engineering - Industrial
Engineering - Manufacturing
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200151912 / Latpro-3739575 
Date posted: Apr-22-2020
State, Zip: California, 95014


Extraction CAD Engineer

Santa Clara Valley (Cupertino) , California , United States



Posted: Feb 17, 2020

Role Number: 200151912

Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role as a team member in our advanced EDA CAD Group, you will improve your career by working on state of the art design technology. You'll have the opportunity to utilize your parasitic extraction experience to develop/define&refine extraction and simulation methodologies for transistor and gate level designs. The areas will include but not limited to capacitance modeling, interconnect parasitic extraction, RC reduction, validation of RC results in field solver etc.

Key Qualifications

  • We are looking for strong engineers with 5+ years of industry experience in parasitic extraction.
  • Device extraction as well as Capacitance Extraction experience.
  • Extraction flow development using StarRCXT/QRC/XRC for transistor level, as well as gate level LVS flows using Calibre/ICV.
  • Strong scripting skills in any of the following: Perl, TCL, SKILL, or C.
  • Experience in the following areas would be a plus: Field solver packages. RC reduction tools.


Responsibilities include: - Development of custom extraction solutions at the gate level and/or transistor level. - Utilizing your hands-on skills to revamp/rewrite and streamline the extraction flow. - Assume ownership of entire extraction flow, working closely with various design groups. (Full-Chip/Custom Digital/Analog) on their extraction requirements for various post layout flows.

Education & Experience

MS/BS Degree in Electrical Engineering, Computer Science or equivalent


See job description


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