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 SoC Physical Design Engineer, Top Level - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
Engineering - Electrical
Engineering - Telecom
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200160876 / Latpro-3739589 
Date posted: Apr-22-2020
State, Zip: California, 95014

Description

SoC Physical Design Engineer, Top Level

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Mar 20, 2020

Role Number: 200160876

In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout.

Key Qualifications

  • The ideal candidate will have 5+ years of hands on experience in physical design and large chip integration.
  • Needs to be familiar with all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
  • Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
  • Familiar with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
  • Must have experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
  • Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz utilizing state of the art sub 45nm technologies.
  • A detailed understanding of database management issues will be required.
  • From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.
  • Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.

Description

  • Work with FE team to understand chip architecture and drive physical aspects early in design cycle.
  • Work with physical design team, drive methodologies and "best known methods" to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.
  • Be focal point for place and route drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route.
  • Resolve design and flow issues related to physical design, identify potential solutions and drive execution.

    Education & Experience

    MSEE or equivalent is required



  • Requirements

    See job description

     

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