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 Design Verification Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
Engineering - Electrical
Engineering - Telecom
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200018991 / Latpro-3739790 
Date posted: Apr-22-2020
State, Zip: California, 95014

Description

Design Verification Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Apr 10, 2020

Role Number: 200018991

At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product.

Key Qualifications

  • Advanced knowledge of standard ASIC design and verification flows including RTL design, simulation and testbench development
  • Solid verification skills in problem solving, constrained random testing, and debugging
  • Experience defining coverage space and writing coverage model a plus
  • Experience with SystemVerilog Assertion (SVA) a plus
  • Team player with excellent communication skills and the desire to take on diverse challenges
  • Experience writing scripts in languages such as Perl or Python
  • Expertise in HVL and HDL (SystemVerilog, Verilog)
  • Advanced knowledge of HVL methodology (UVM/OVM)

Description

Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development. Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage. Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model, and improve methodology. Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.

Education & Experience

BSEE or MSEE



Requirements

See job description

 

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