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 CSM Display Analog Lead - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
Engineering - Electrical
Engineering - Telecom
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200006730 / Latpro-3739811 
Date posted: Apr-22-2020
State, Zip: California, 95014


CSM Display Analog Lead

Santa Clara Valley (Cupertino) , California , United States



Posted: Nov 16, 2018

Role Number: 200006730

Are you a leader? Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies. The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV. We are looking for a remarkable Analog Design Lead to work with multi-functional teams and external vendors to define, develop and productize the next generation of custom silicon for Apple products.

Key Qualifications

  • We are looking for applicants with 10+ years of experience with proven track record of developing leading integrated solutions implemented in silicon for the mobile market with the following experience:
  • 2+ years of technical management experience.
  • Direct experience and in depth understanding of analog design specifically op-amps, LDO, PMU, PLL, high-speed CDR and SERDES.
  • Hands-on design experience with Cadence schematic capture and simulation tools.
  • Experience with all phases of product development cycle from definition to transfer to production.
  • Hands-on experience with analog circuit design, chip integration, verification and validation.
  • Direct involvement with ATE test plan development, review of results and limit setting.
  • Familiarity with Digital design and PCB signal integrity is a plus.


Imagine yourself at the center of our hardware development effort. Where you will collaborate with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with vendors to promote efficiency in the Silicon community. We value your technical understanding of analog design principles. Here are the main responsibilities of this role: - Support Subsystem Engineering groups during engineering specification development and feasibility studies. - Technical management of ASIC suppliers. - Establish and review the simulation methodology and verification requirements. - ASIC Development schedules. - Establish design review report format and perform systematic review of simulations details. - Analyze the circuit designs and ensure robustness of designs. - Review T/O verification reports. - Review and provide feedback to the vendors about their bench validation and ATE test plans, limits and statistical data. - Provide support to subsystem engineering teams for analog issues of ASICs, Signal Integrity and components. - Work with multi-functional teams on analog issues. - Co-simulate circuits in Cadence environment.

Education & Experience

BSEE / MSEE is required, PhD preferred.

Additional Requirements

  • Some Travel Required.
  • Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.


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