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 GPU Top Level Physical Design Engineer - Austin, Texas, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Electronics
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200012338 / Latpro-3739817 
Date posted: Apr-22-2020
State, Zip: Texas, 78729

Description

GPU Top Level Physical Design Engineer

Austin , Texas , United States

Hardware

Summary

Posted: Nov 13, 2018

Role Number: 200012338

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, large subsystems. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll craft and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout.

Key Qualifications

  • We value your hands on experience in physical design and large chip integration.
  • Are you familiar with all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration?
  • Showcase your knowledge of typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
  • Familiar with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
  • Your depth of expertise on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain will serve you well.
  • Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz utilizing state of the art sub 45nm technologies.
  • We would like you to join our team if you have detailed understanding of database management issues.
  • From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.
  • Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.

Description

Collaborate with FE team to understand chip architecture and drive physical aspects early in design cycle. Help push innovation with the physical design team, as you drive methodologies and "best known methods" to streamline PD work. Develop up with guidelines and checklists, drive execution, and track progress. Be the focal point for place and route. Drive the work among PnR engineers to set goals, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. Reach new career highs as you resolve design and flow issues related to physical design, identify potential solutions and drive execution Are you a confident problem solver who thrives under pressure to find new, creative solutions? Are you ready to help chart the future of Apple's ecosystem? If so, we are excited to hearing from you.

Education & Experience

MSEE or equivalent is required



Requirements

See job description

 

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