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 SerDes Circuit Designer - Austin, Texas, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200002012 / Latpro-3739856 
Date posted: Apr-22-2020
State, Zip: Texas, 78729

Description

SerDes Circuit Designer

Austin , Texas , United States

Hardware

Summary

Posted: Feb 7, 2020

Role Number: 200002012

At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and especially talented SerDes Circuit Designer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Apple Silicon Engineering is seeking qualified SERDES designers to work on the next generation SERDES PHYs for Apple's world-leading systems-on-chip (SOCs). You will be part of a growing analog/mixed-signal team involved in design and productization on leading-edge CMOS process technology nodes.

Key Qualifications

  • - The ideal candidate should have experience in high-speed serial links with expertise in the following: Very knowledgeable about high-speed SerDes protocols (e.g., PCIe, USB, SATA, etc.).
  • - Strong knowledge of analog CMOS designs and topologies. Experience with Tx/Rx equalization techniques and circuits.
  • - Experience with high speed digital circuit (e.g., serializer, deserializer, counters, dividers, etc.) design, analysis and verification (e.g., STA, formal verification).
  • - Experience in analyzing link jitter budget for high-speed serial links and creating block level requirements.
  • - Knowledge of different CDR architectures.
  • - Experience in lab testing of high-speed serial links and defining equipment needs.
  • - Experience in the following areas is helpful: Able to think outside of the box and come up with creative solutions.
  • - Static timing analysis tools (e.g., Nanotime, Primetime, etc.).
  • - Modeling of CDR and adaptive loops (using C, Matlab or Python, etc.).
  • - Able to create VerilogA/AMS behavioral models. Knowledge of ESD requirements.

Description

Ownership of analog and digital circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, clock generation and distribution, etc.). You will interact with cross-functional teams to define requirements/specs (e.g., modeling, package, board, DFT, ESD, etc.). Create block-level specifications based on link-budget, behavioral modeling, and transistor-level feasibility. Work closely with mask design to implement layout view of designs. Generation/QA of various IP Kit views/files for release to IP consumers. Defining production/bench-level testplans. Hold design reviews of blocks with peers/management to show design meets spec targets and requirements.

Education & Experience

The minimum requirements for this role are an MSEE plus 7 years' experience or PhD with 5 years relevant experience.



Requirements

See job description

 

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