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 CSM Design Verification Lead - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Creative services/Design
Engineering - Electrical
Engineering - Telecom
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200006690 / Latpro-3739912 
Date posted: Apr-22-2020
State, Zip: California, 95014

Description

CSM Design Verification Lead

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Nov 1, 2018

Role Number: 200006690

Are you a leader? Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies. The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV. We are looking for a remarkable Design Verification Lead to work with multi-functional teams and external vendors to define, develop and productize the next generation of mobile power solutions.

Key Qualifications

  • Advanced knowledge of SOC/Display/Audio & System architecture/design & in-depth knowledge of the state of the art verification flow.
  • Experience with verification environment, including System Verilog / UVM / VMM.
  • Knowledge of industry standard interfaces, deep understanding of Verilog, Verilog simulator and debug.
  • Clear understanding of constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.
  • Knowledge of Formal verification, low power verification and analog mixed signal simulation are a plus.
  • Should be a phenomenal teammate with excellent social skills and the passion to take on diverse challenges.

Description

You will be responsible for ensuring the quality of the chip & is expected to: - Work closely with internal & external teams to review specifications, improve DV plans & methodologies, and ensure full test coverage. - Collaborate with design & micro-architecture teams to understand the functional & performance goals of the design. - Lead and track DV progress. Review DV metrics. Provide technical guidance to DV implementation and execution. - Have strong communication skills, reciprocal approaches, and excellent multi-functional capabilities.

Education & Experience

BSEE / MSEE or MSCE with industry experience over 10 years.

Additional Requirements

  • Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.





Requirements

See job description

 

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