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 ASIC Design Engineer - Memory Controller - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Platforms
Electronics Manufacturing
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200003656 / Latpro-3740321 
Date posted: Apr-30-2020
State, Zip: California, 95014

Description

ASIC Design Engineer - Memory Controller

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: May 1, 2020

Role Number: 200003656

Imagine what you could do here. At Apple, new ideas have a way of becoming great products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Apple is building the world's fastest highly-parallel mobile processing systems. Our high-bandwidth multi- client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will be working with a world-class memory subsystem design team delivering dram controller, cache, switch etc. You will also be directly responsible for designing and delivering a deeply high-performance memory controller design for the next generation of Apple application processor architecture.

Key Qualifications

  • A proven history of technical leadership:
  • 3+ years of architecture research and/or development of memory or highly interconnected system architectures.
  • 3+ years of RTL/micro-architecture definition.
  • Knowledge of high performance memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram interface calibration/training mechanisms and algorithms is a plus.
  • Systems experience in characterizing performance, doing comparison studies, and documenting and publishing results.

Description

Drive new memory system architectures from DRAM up. Explore architecture and feature trade-offs in system performance, area, and power consumption. Develop memory hierarchies for high performance parallel computer architectures (system-on-a-chip SOC). Work with performance team to develop performance/power simulators, models and test suites.

Education & Experience

Bachelor's or Master's degree in CS/CE/EE



Requirements

See job description

 

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