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 CPU Cache RTL Architect - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Software Engineer
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200171105 / Latpro-3741335 
Date posted: May-15-2020
State, Zip: California, 95014


CPU Cache RTL Architect

Santa Clara Valley (Cupertino) , California , United States



Posted: May 15, 2020

Role Number: 200171105

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products! We are looking for an experienced engineer that can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.

Key Qualifications

  • The ideal candidate should possess 5-10+ years of CPU RTL and architecture experience.
  • Knowledge and experience with the following as it relates to CPU cache design:
  • Coherence protocols and interconnects
  • High performance (low latency, high bandwidth) design techniques
  • Memory subsystem queuing, scheduling; starvation and deadlock avoidance
  • SRAM design basics
  • Multiple clock/power domains and power management strategies
  • Prefetchers, replacement policies
  • Debug capabilities
  • DFT strategies
  • Error detection and correction
  • Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools. Experience in C or C++ programming and interpretive languages such as Perl or Python.
  • Knowledge of logic design principles along with timing and power implications and understanding of low power microarchitecture techniques.


As a cache subsystem architect you will own or participate in the following: - Microarchitecture development and specification. From early high-level architectural exploration, through microarchitectural research and arriving at a detailed specification. - RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. - Performance exploration. Explore high performance strategies and work with the verification team to validate that the RTL design meets targeted performance. - Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.

Education & Experience

BS/MS in Computer or Electrical Engineering is required.


See job description


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