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 Senior Standard Cell Circuit Design Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200001970 / Latpro-3741341 
Date posted: May-15-2020
State, Zip: California, 95014

Description

Senior Standard Cell Circuit Design Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: May 7, 2020

Role Number: 200001970

Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking. Join us, and you'll help design the tools that allow us to bring customers experiences they've never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Senior Standard Cell Circuit Design Engineers! In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact delivering products to market quickly.

Key Qualifications

  • We are looking for applicants with 10+ years of experience in Custom/Semi-Custom Circuit Design for Low Power and High Performance Blocks.
  • Good understanding of transistor level design, analysis and optimization.
  • Proven experience with architectural path optimization for CPU, Graphics and/or SOC applications.
  • Experience with PPA evaluation using different libraries, templates and circuit topologies.
  • Good understanding of cell characterization and library validation flows.
  • Experience with various EDA tools for synthesis, place-route, verilog simulation, spice simulation, formal verification, DRC/LVS, RC extraction and/or library characterization.
  • Familiarity of Verilog syntax, liberty models and variation format.
  • Knowledge of timing, power, noise and IR analysis.

Description

Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. You will perform the following: - Define and Develop complex standard cells/semi custom designs that significantly boosts circuit performance in advanced technologies, while optimizing dynamic/static power consumption - Engage with chip design teams to understand new library requirements, identify PPA opportunities by developing custom circuit options - Analyze and develop robust circuits that operate at very low voltages. - Identify circuit techniques that provide systemic power reduction. - Engage with timing teams, chip design leads to identify key requirements from STA, crosstalk, EMIR, P&R flows perspective

Education & Experience

BSEE / MSEE is required.

Additional Requirements

  • Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.





Requirements

See job description

 

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