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 Compute HW Architect (SPG) - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Engineering - Electrical
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200172507 / Latpro-3742106 
Date posted: May-27-2020
State, Zip: California, 95014


Compute HW Architect (SPG)

Santa Clara Valley (Cupertino) , California , United States



Posted: May 26, 2020

Role Number: 200172507

The compute hardware architecture team in the Special Projects Group is responsible for the definition, specification and technical leadership for the end-to-end compute needs of next generation autonomous systems. We are looking for talented candidates with strong hardware architecture expertise (CPU, GPU and hardware accelerator) and familiarity with signal processing, computer vision and machine learning algorithms. The role requires analysis of algorithms to define compute partitioning between compute resources (CPU, GPU, hardware accelerators), and definition of specialized hardware accelerators or enhancements to existing ones. Does working on autonomous technology excite you? If you're passionate about the user experience, want to be part of a group that works on very early stage products, have the opportunity to shape them, and enjoy crafting robust, scalable, and maintainable services, we may be the team for you!

Key Qualifications

  • Extensive experience inefficient hardware architecture implementations of computer vision, machine learning and signal processing algorithms.
  • Solid understanding of the tradeoffs between CPU, GPU, and hardware accelerator implementations.
  • Ability to bench mark algorithms on CPUs and GPUs; analyze performance counters and create high-level algorithm complexity models.
  • System-level knowledge of tradeoffs of heterogeneous and interconnected compute resources.
  • Demonstrated ability to develop hardware accelerator performance and bit accurate models in high level programming languages.
  • Strong object-oriented programming experience in C++,Python, Swift or equivalent high-level languages.
  • Familiarity with digital design of hardware accelerator for FPGA or ASIC.
  • Excellent communication skills required to interact with cross functional teams from algorithms and software to hardware micro-architecture and circuit design teams.


Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

Education & Experience

- Ph.D. EE/CE/CS, or M.S. EE/CE/CS with 5+ years of relevant industry experience


See job description


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