CPU Implementation Lead Engineer
Santa Clara Valley (Cupertino) , California , United States
Posted: Jul 21, 2020
Role Number: 200182453
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! Apple's Silicon Engineering Group (SEG) is hiring experienced engineers for the CPU Implementation leadership team.
- The ideal candidate should possess a MS or PhD in Electrical Engineering with 10+ years of CPU Implementation experience.
- Experience in driving chip implementation (preferably CPUs) from definition phase to silicon correlation
- Familiarity with high performance microprocessor architecture fundamentals
- Knowledge of logic design principles along with timing and power implications
- Understanding of low power microarchitecture and implementation techniques
- Design experience in deep submicron technologies and basic transistor level design and device physics
- Experience using synthesis & place-route tools
- Experience with scripting in Perl and/or TCL
As a CPU Implementation Lead Engineer, you will own or participate in the following: - CPU IP delivery. Work with multi-functional engineering teams to implement and validate physical design in the aspects of timing, power, area, electrical analysis, functionality, reliability, and testability. - Work extensively with the partition implementation team to make area/frequency/performance/power tradeoffs and remove bottlenecks in meeting design targets and delivery schedule. - Participate in the definition and enhancement of RTL-to-GDS flow through synthesis and place-and-route targeting aggressive targets for power, performance, and area. - Direct and mentor junior engineers.
Education & Experience
BSEE/MSEE is required.