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 Pixel IP Performance Architect - Platform Architecture - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Other
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200197086 / Latpro-3756934 
Date posted: Oct-06-2020
State, Zip: California, 95014

Description

Pixel IP Performance Architect - Platform Architecture

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Oct 5, 2020

Role Number: 200197086

Do you love crafting elegant solutions to highly complex challenges? Are you a big-picture forward-thinking who understands how each element affects all the others? At Apple, our Architecture group is responsible for connecting our hardware and software into one unified system. Join this team, and you'll collaborate with engineers across Apple to design how all of our technologies work in unison! In this highly visible role, you will lead the Performance Modeling of SoC pixel subsystem.

Key Qualifications

  • The ideal candidate will have 5+ years of in chip architecture or performance modeling
  • SoC pixel subsystem architecture and micro-architecture knowledge
  • Experience in performance modeling environment
  • Knowledge and experience in common performance benchmarks and workloads
  • Proficiency in software development in C/C++
  • Proficiency in scripting languages such as Python or Perl
  • Experience in document architecture specifications

Description

The ideal candidate will be responsible for all aspects of SoC pixel subsystem performance. Responsibilities include: collaborate with cross-functional teams such as platform architecture, micro-architecture, software teams to set and document performance targets and details for important use cases, analyze workloads to identify performance bottlenecks and opportunities, perform performance simulations of alternative designs, develop and implement C++ model and interface it to the agent models and software simulation platforms, develop tests representing use cases to run on the performance models, correlate performance of the RTL infrastructure with the C++ model, and document the architectural performance models.

Education & Experience

BSEE/CE required. MSEE/CE preferred.



Requirements

See job description

 

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