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 RFIC Layout Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Engineering - Telecom
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200198220 / Latpro-3757365 
Date posted: Oct-09-2020
State, Zip: California, 95014

Description

RFIC Layout Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Oct 8, 2020

Role Number: 200198220

Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products.

Key Qualifications

  • You will have the following qualifications:
  • Experience in custom RF/analog layout with extensive knowledge of deep sub-micron CMOS (40nm, 28nm, FinFET, etc.)
  • Knowledgable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing
  • Solid understanding of RC delay, electromigration, and coupling
  • Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
  • Knowledge of CADENCE layout tools
  • Excellent communication skills and able to work with cross-functional teams
  • You would also have the following, if you're more experienced:
  • Capability to lead other layout engineers for top-level integration
  • Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems
  • Scripting skills in PERL or SKILL are a plus, but not required

Description

As a RF layout engineer, you will be responsible for:

  • Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
  • Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM checking
  • Co-work with designers on block level and top-level floorplanning
  • Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling
  • Top-level layout integration and verification, schedule management

    Education & Experience

    BSEE preferred

    Additional Requirements

    • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.





  • Requirements

    See job description

     

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