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 PD CAD Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200199832 / Latpro-3758244 
Date posted: Oct-16-2020
State, Zip: California, 95014

Description

PD CAD Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Oct 15, 2020

Role Number: 200199832

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a member of the CAD team, you will create and support innovative physical design methodology and CAD flow. You will collaborate with physical design teams, CAD teams, and EDA vendors.

Key Qualifications

  • Typically requires 3+ years experience in P&R and flow development.
  • Understand various aspects of partition level PNR including floorplanning, power planning, placement, timing/power optimization, CTS, routing, UPF
  • Understanding and exposure to extraction and timing analysis flows
  • Understand hierarchical P&R issues is a key (top-level floor planning, pin-assignment, clock-distribution, UPF, power-distribution, multi-voltage design, pad ring construction, placement, optimization, and routing)
  • Strong TCL/Perl/Python/Makefile scripting knowledge.
  • Proven track record of managing, and regressing P&R flows.
  • You should be familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies.
  • We are looking for a self-motivated, dedicated problem solver. Strong interpersonal/communication skills are a requirement.
  • Innovus or ICC knowledge is a plus.

Description

- Provide innovative solutions to support and improve the quality of physical design. - Work with chip design teams to implement and customize design flows that are optimal for a given chip - Provide documentation, training, and new-user-support. - Responsible for diagnosis, resolution, and regression of reported problems.

Education & Experience

BS/MS in EE/CS or equivalent.



Requirements

See job description

 

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