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 GNSS Wireless Design Verification Engineer - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Engineering - Telecom
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200199958 / Latpro-3758379 
Date posted: Oct-17-2020
State, Zip: California, 95014


GNSS Wireless Design Verification Engineer

Santa Clara Valley (Cupertino) , California , United States



Posted: Oct 16, 2020

Weekly Hours: 40

Role Number: 200199958

Would you like to join Apple's growing wireless silicon development team? Global Navigation Satellite Systems (GNSS) space vehicles transmit the power of a lightbulb, they are 13000 miles away, and are moving four kilometers per second. The received signals are commonly one hundred times weaker than cosmic microwave background radiation left over from the Big Bang and arrive next to interfering signals ten billion times stronger, just few MHz away. Our GNSS team is part of Apple's wireless SOC team. We are a vertically integrated engineering team spanning RF, mixed signal analog design, systems engineering, Design Verification, RTL design, firmware and software engineering, Test, and Validation. Our focus is on highly energy efficient and robust GNSS receiver design. We develop GNSS technology that touches hundreds of millions of lives, something we are passionate about. We'd like you to consider being a part of our team. As a GNSS Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of our GNSS IP and SoC subsystem. As part of our DV team, you will develop reusable testbench and verification environment deploying the latest methodology, working closely with GNSS and SoC front-end designers and Systems Engineers.

Key Qualifications

  • 4+ years Wireless/DSP block/system verification experience.
  • Advanced knowledge of SystemVerilog and DV methodology.
  • Solid verification skills in problem solving, constrained random testing, and debugging.
  • Knowledge of GNSS and SOC subsystem verification experience are desirable.
  • Experience with SystemVerilog Assertion (SVA) a plus.
  • Strong verbal and written communication skills are needed.


  • Build block / subsystem / chip level testbench using best in class DV methodologies.
  • Build verification plan from specification and review with designers and systems engineers.
  • Architect testbench with maximum reusability in mind and create UVM libraries.
  • Generate directed and constrained random tests, debug failures, manage bug tracking, and close coverage.
  • Create and analyze block/subsystem level coverage model and add test cases to increase coverage.

    Education & Experience

  • A BS degree in Electrical Engineering is required; a M.Sc. degree is desirable.

  • Requirements

    See job description


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