Cellular SOC Design Verification Engineer
Santa Clara Valley (Cupertino) , California , United States
Posted: Oct 19, 2020
Weekly Hours: 40
Role Number: 200200533
Do you have a passion for invention and self-challenge? This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Apple's Silicon Engineering Group has embarked upon to date. As part of our team, you will have the opportunity to take the lead on and contribute to verifying a set of complex SOCs. This team will allow you to integrate multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development groups across Apple, you can push the industry boundaries of what cellular systems can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a large scale SOC, different types of SOC architecture, many high speed layered protocols, industry's standard methodologies on low power architecture, best in class DV methodology, verification on accelerated platforms, knowledge on Cellular protocol, FW-HW interactions, complexities of multi-chip SOC debug architecture, etc. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state-of-the-art Cellular SoCs! This position requires someone comfortable will all areas of SoC design verification engineering. Someone that thrives in a dynamic multi-functional organization, is not afraid to debate ideas openly, and is flexible enough to pivot on constantly evolving requirements.
- 5+ years of dedicated/hands-on ASIC DV experience.
- Advanced knowledge of HVL methodology (UVM/OVM) with most recent experience in UVM.
- Proven track record of working full ASIC cycle from concept to tape-out to bring-up.
- Experience taping out large SOC systems with embedded processor cores.
- Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
- In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.
- Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.
Understand details of High Efficiency SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, DDR, Memory Controller Sub Systems, USB, PLL, power up, Secured Boot schemes. Create coverage driven verification plans from specifications, review and refine to achieve coverage targets. Create IP level module and sub-system verification plan, TB, portable test benches, sequences, test infrastructure. Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level, achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify overall SOC design. Work closely with DV methodology architects to improve verification flow.
Education & Experience
Typically requires MSEE or beyond