Analog Mixed Signal IP Integration Engineer
Santa Clara Valley (Cupertino) , California , United States
Hardware
Summary
Posted: Oct 21, 2020
Weekly Hours: 40
Role Number: 200198328
In this highly visible role, you will support the integration of 3rd party analog IP in the SOCs developed by Apple. Your job is to verify that the IP deliverables are meeting Apple's high quality standards and get flawlessly integrated. The role involves working closely with different cross-functional teams within Apple as well as with external vendors. Occasional travel might be required
Key Qualifications
- Min 7 years experience in IC design
- Experience with the design or integration of SERDES, DDR PHY, PLL, ADC, DAC, Thermal sensor, LDO, DC-DC converter, charge pump
- Solid background in circuit design to understand transistor-level circuit schematics and analyze verification results
- Familiarity with both the SOC design flow and analog design flow, also with verification methodologies
- Deep knowledge and experience in with front-end tools such as Digital and Analog simulation, waveform viewers, synthesis, lint, logic equivalence, static timing analysis, CDC, RDC, UPF, version control
- Good understanding of digital timing and DFT requirements for SOCs
- Experience with Verilog modeling and model validation
- Experience writing Verilog, SystemVerilog, SVA and Verilog-AMS hardware description languages
- Experience with standards like PCI Express, MIPI, USB or DisplayPort is a plus
- Excellent written and verbal communication skills
- Strong initiative and ownership of responsibilities, productive, able to meet aggressive deadlines
Description
You will be part of a small team responsible for 3rd party analog IP. Your role will be: Defining and specifying deliverable requirements for analog IP provided by external vendors, driving discussions with vendors, regarding these requirements. Reviewing their designs and modeling methodology. Running QA checks on incoming IP deliverables. Providing support to the Apple SOC front-end and backend design teams for integrating the analog IP
Education & Experience
BSEE / MSEE is required
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