Design Verification Engineer
Santa Clara Valley (Cupertino) , California , United States
Posted: Oct 22, 2020
Role Number: 200201374
At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. This role is for a digital-focused DV engineer who will enable us to produce fully functional first silicon for mixed-signal designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
- Sophisticated knowledge of SystemVerilog and UVM
- Deep knowledge in developing scalable and portable test-benches
- Relevant experience with verification methodologies and tools such as simulators, waveform viewersBuild and run automation, coverage collection, gate level simulations
- Deep UVM knowledge, C/C++ experienced level knowledge
- Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR
- Basic knowledge of formal verification methodology
- Some experience with power-aware (UPF) or similar verification methodology
- Excellent knowledge of one of the scripting languages such as Python, Perl, TCL
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will learn to develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.
Education & Experience
Master's Degree or Bachelor's Degree in technical subject area.