Design Verification Engineer
Santa Clara Valley (Cupertino) , California , United States
Posted: Oct 22, 2020
Role Number: 200201389
At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and unusually talented Design Verification Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Do your life's best work here at Apple! This role is for a DV engineer who will enable bug-free first silicon for the mixed-signal designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
- Deep knowledge of System Verilog test-bench language and UVM
- Proven experience developing scalable and portable test-benches
- Proven experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
- Experience with mixed signal verification methodology
- In lieu of UVM knowledge, C/C++ expert knowledge
- Significant experience with DDR PHY or Controller
- Deep knowledge of one of the scripting languages: Python, Perl, TCL
- Deep knowledge of formal verification methodology
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal designs.
Education & Experience
Masters + 3 years industrial experience Bachelors + 5 years industrial experience