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 Timing Design Engineer - San Diego, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200201349 / Latpro-3759093 
Date posted: Oct-22-2020
State, Zip: California, 92101

Description

Timing Design Engineer

UTC

San Diego , California , United States

Hardware

Summary

Posted: Oct 22, 2020

Role Number: 200201349

At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and extraordinarily talented Timing Design Engineer. As a member of our multifaceted group, you will have the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every day. In this role, you will be at the center of a PHY design effort collaborating with architecture, CAD, logic design teams, with a critical impact on delivering outstanding PHY designs. You will be directly involved in timing closure and/or physical designs of outstanding PHY design.

Key Qualifications

  • - Preferred at least 5+ years of Physical Design experience on high PHY and/or SOC designs
  • - Deep knowledge of industry standards and practices in Timing closures, Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route Experience in developing and implementing STA constraints
  • - Deep understanding of all aspects of Timing flow, Physical construction, Integration and Physical Verification
  • - Confirmed knowledge of Basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixes
  • - Experienced user of industry standard Timing, Physical Design and Synthesis tools
  • - Deep Understanding of scripting languages such as Perl/Tcl

Description

As a Timing Design engineer you will be involved with all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block level static timing constraints. Close timing on critical blocks by working with RTL, PD teams. Develop and validate high performance low power clock network guidelines. Perform Timing optimization and implement the design for functionality. Generate and Implement ECOs to fix timing etc. Run Timing verification flow at chip/block level and provide guidelines to fix violations to other designers and/or perform the fixes. Participate in establishing CAD and physical design methodologies for accurate by construction designs. Assist in flow development for chip integration.

Education & Experience

Bachelor or Master's degree in Electrical Engineering is required



Requirements

See job description

 

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