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 PHY RTL Design Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Engineering - Telecom
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200201598 / Latpro-3759163 
Date posted: Oct-23-2020
State, Zip: California, 95014

Description

PHY RTL Design Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Oct 22, 2020

Role Number: 200201598

Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a critical impact on getting functional wireless products to hundreds of millions of customers quickly.

Key Qualifications

  • 3+ years of verification experience of wireless/wired communication block/subsystem.
  • Excellent knowledge and experience of ASIC verification flow including test bench development, constrained random testing, and code/functional coverage.
  • Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
  • Experience of using Matlab/C reference model and bit-accurate verification a plus.
  • Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.
  • Proficient in shell and Perl scripting, Python skills a plus.
  • Experience of Palladium/FPGA validation a plus.
  • Should be a team player with excellent communication skills, self-motivated and well organized.

Description

Develop signal processing intensive design for wireless communication SoCs, including: - Writing specifications and other documents based on MATLAB/C system model - Microarchitecture definition - IP integration, RTL logic design, and DV support - Running tools to ensure lint-free and CDC clean design - Synthesis and timing constraints - Work with algorithm and software team to ensure performance and power efficiency

Education & Experience

MSEE, Ph.D. preferred



Requirements

See job description

 

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