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 Wireless Design Verification Engineer - San Diego, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Engineering - Telecom
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200201786 / Latpro-3759269 
Date posted: Oct-23-2020
State, Zip: California, 92101

Description

Wireless Design Verification Engineer

San Diego , California , United States

Hardware

Summary

Posted: Oct 23, 2020

Role Number: 200201786

Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of communication subsystem including MAC, PHY, and interfaces. With deep understanding of communication systems and protocols, you will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Key Qualifications

  • 7+ years Wireless/Wired communication block/system verification experience.
  • Advanced knowledge of SystemVerilog and DV methodology.
  • Solid verification skills in problem solving, constrained random testing, and debugging.
  • Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.
  • Experience with MAC or PHY Verification a plus.
  • Experience with SOC subsystem verification a plus.
  • Experience with SystemVerilog Assertion (SVA) a plus.
  • Should be a team player with excellent communication skills and the desire to take on diverse challenges.

Description

- Build block / subsystem / chip level testbench using best in class DV methodology. - Build verification plan from specification and review with designers and systems engineers. - Architect testbench with maximum reusability in mind, and create UVM libraries. - Generate directed and constrained random tests. - Debug failures, manage bug tracking, and close coverage. - Create and analyze block/subsystem level coverage model, and add test cases to increase coverage. - Attend verification reviews and set standard for coding quality. - Work closely with DV methodology architects to improve verification flow.

Education & Experience

MSEE and beyond preferred.

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.





Requirements

See job description

 

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