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 Senior Chip Integration Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200201812 / Latpro-3759277 
Date posted: Oct-23-2020
State, Zip: California, 95014

Description

Senior Chip Integration Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Oct 23, 2020

Weekly Hours: 40

Role Number: 200201812

At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. As a digital IC Design Engineer, your primary responsibility will be RTL design. This will include block/function definition, specification, design, and unit level verification of digital functions. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product.

Key Qualifications

  • This position requires thorough knowledge of the ASIC design flow, FE and Design verification, synthesis, scripting and netlist generation. The ideal candidate will have the following background
  • At least 8+ years' experience in ASIC design flow
  • Proven track record of high performance designs in high volume production for low power applications
  • Proven track record of RTL design and timing closure on large complex designs
  • Expertise in:
  • SOC IP integration and RTL Design for performance, low area, and low power
  • FE production synthesis with DFT insertion
  • ASIC design flow and netlist flow checks - CDC, Logical Equivalence
  • UPF flow for power islands as well as voltage islands
  • Design interfacing to PD for floor planning and timing closure
  • Strong communication skills are a must as the candidate will interface with a lot of different groups within and outside the company
  • Self-starter, highly motivated, highly organized, and schedule driven is a mustFamiliarity with DFT and backend related methodology and tools is ideal

Description

You will be responsible for the following: Own all aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control bus logic for connectivity of IP blocks to main SOC infrastructure, ownership of the Integration Spec for the design project, integration and optimization of any memories and hard macros required for the block, run synthesis, netlist generation, and timing closure for the block Work closely with Chip Architecture, Design verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs Develop and maintain methodology/flows/checks for your design Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process

Education & Experience

BSEE/MSEE in a relevant area. PhD Preferred. 10+ years of experience



Requirements

See job description

 

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