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 Silicon Validation PVT Engineer - PDX - Portland, Oregon, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Software Engineer
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200203343 / Latpro-3760135 
Date posted: Oct-30-2020
State, Zip: Oregon, 97201


Silicon Validation PVT Engineer - PDX

Portland , Oregon , United States



Posted: Oct 29, 2020

Role Number: 200203343

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. As part of Silicon Validation Team, you will focus on silicon validation, debug and root cause related to anomalous behaviors using system work-loads. (circuit marginalities, process-design interactions, logic bugs).

Key Qualifications

  • Exposures to post-Silicon validation, silicon bringup, testing/debug/root cause of circuit marginalities, product engineering, foundry manufacturing, etc.
  • Understanding test execution through both functional mode and DFX hooks
  • You are comfortable working primarily in a lab environment
  • You have strong scripting skills in one of the major languages: eg. Perl, python, Tcl, bash
  • You have good experimental technique, techniques of problem localization and root-cause
  • You have system level understanding of CPU/SoC architecture, Memories (DDR, NAND), Systems
  • Good data analysis skills and attention to details
  • Nice-to-haves (in at least one and preferably several areas):
  • Chip design background in circuit/physical design (timing closure, power, etc.) or DV (correlating SW signatures to block level tests).
  • Post silicon physical debug background in speed-path/Vmin, memory arrays, clocking or yield improvements.
  • Post silicon logic debug background in exercising various DFX features, analyzing scandump/memdump, suggesting tests in both system level or to DV
  • Deep understanding of boot process, boot-loaders, embedded software, micro-kernel and able to tweak system tests.
  • Product engineering background and familiarity with ATE coverage, margin, binning, scan pattern generation, etc.
  • Good IP knowledge in some PHY blocks (eg. DDR, PCIe, USB, etc)


In this role, you will own and execute on the post silicon validation and characterization test plans across Process, Voltage and Temperature (PVT), debug various issues encountered along the way (setup artifacts, test code, logic bugs, physical design debugs, etc. TASKS WILL INCLUDE: - Understanding new chip features and define coverage applicable to our test environment - Executing a validation test on large volume and analyze results (pass/failure/artifacts/surprises/etc.) - Be the first line of defense when failure occurs to isolate (setup, code, artifacts, silicon issues, logic/physical, identify blocks, etc.). - Once isolated, working with domain experts to define debugs and come up with a root cause. - Assisting in driving a fix. Maintain and create automation scripts/flows for self consumption as well as others. - Able to summarize debugs/findings and think along the line of improvements in both DFX features and test coverage.

Education & Experience

BS/MS in Computer Engineering or Electrical Engineering or equivalent is required.


See job description


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