Senior Standard Cell APR - QA Engineer
Santa Clara Valley (Cupertino) , California , United States
Posted: Oct 30, 2020
Role Number: 200013989
Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you'll help design the tools that allow us to bring customers experiences they've never before envisioned. We have an extraordinary opportunity for Senior ASIC design engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on silicon validation, making a critical impact delivering products to market quickly.
- Hands on experience in library development, understanding of EDA views and their interaction with physical design flows.
- Familiar with development of testchip block for silicon validation of stdcells and megacells.
- Familiarity of ASIC integration flows including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
- Familiarity with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies.
- Proficiency in: static timing analysis, Verilog/VHDL, formal verification, lint checks, multi-clock and power domain designs.
- Strong written/verbal communication skills.
- Experience with ECO implementation, both functional and timing closure.
- Familiarity with DFT insertion, and multi-mode timing constraints.
Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. In this role, you will be responsible for fully comprehensive library EDA view validation, by taking a P&R block through RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing optimization, leakage recovery and closure and signoff. You will also be responsible for PT/spice correlation, signal and power EM analysis, IR analysis and PDV. You will also architect and compose block consisting of library cells for complete Silicon Validation.
Education & Experience
BSEE / MSEE is required.
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.