Mixed Signal Verification Engineer
Santa Clara Valley (Cupertino) , California , United States
Posted: Nov 2, 2020
Role Number: 200204136
Imagine what you could do here at Apple! Together we could help craft the next generation of the world's finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. The Verification team is searching for a self-motivating, passionate electrical engineer for the role of Mixed Signal Verification Engineer. As a member of the Verification team, Apple is looking for a strong candidate who can take on diverse challenges in verifying digital/mixed-signal designs. In this highly visible role, you will be at the center of chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly. You will become part of a hands-on development team that fosters engineering excellence, creativity and innovation. Collaboration across teams is a key component of success at Apple. The right candidate will thrive in that type of environment. You will work with us from Apple's headquarters in Cupertino, California. It's one of the most exciting aspects of the job. Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you help us design the next generation of revolutionary Apple products? Do you have the following qualifications or experience?
- We typically require at least 8 years of experience, and we are looking for individuals with validated experience taking chips to production.
- Experience in the verification of complex mixed signal ICs
- Solid understanding of SystemVerilog from verification point of view
- Extensive experience in creating and using UVM testbenches for mixed signal systems
- Experience in UVM-AMS will be a plus
- Experience in creating test scenarios for complex ICs from the specifications
- Hands-on experience with Analog Assertion Based Verification
- Understanding of analog/mixed-signal blocks like analog/digital PLLs, ADC, DAC, LDO
- Experience in verifying DSP blocks
- Experience in using SV-real, and SV-UDN (User Define Nettype) models in verification
- Experience with wreal and Verilog-A/MS will be a plus
- Experience in RF/MW verification will be a plus
- Experience with power aware verification with UPF will be a plus
- Experience in writing scripts in languages such as Perl or Python
- Excellent teammate with excellent communication skills
As a Mixed Signal Verification Engineer, you will be responsible for performing the verification on digital/mixed signal designs including: - Creating the UVM testbenches for mixed signal blocks - Developing the test scenarios and scoreboards/checkers/assertions based on the design specifications - Working with design and DMS modeling teams to make sure there are no gaps in verification
Education & Experience
MSEE with 8 years of mixed-signal verification experience.