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 ASIC IO Design Verification Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200204724 / Latpro-3760641 
Date posted: Nov-04-2020
State, Zip: California, 95014

Description

ASIC IO Design Verification Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Nov 3, 2020

Role Number: 200204724

Imagine what you could do here. At Apple, great ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. The high-speed serial interfaces of our chips are the critical information pipeline to other chips in the system. As a team member, you will craft models of these interfaces, devise new approaches to test those interfaces, and collaborate to find solutions to any design flaws before silicon fabrication.

Key Qualifications

  • Deep understanding of USB or PCI Express.
  • Familiarity with all aspects of pre-silicon design verification.
  • History of building high quality UVM based verification environments.
  • Deep understanding on constrained random verification techniques.
  • Knowledge of functional coverage.
  • Knowledge of assertion methodology.
  • Excellent interpersonal skills and the dream to face diverse challenges.

Description

As part of the IO verification team you are at the heart of the chip design effort collaborating with all silicon engineering disciplines to get functional and secure products to millions of customers quickly. You will be responsible for ensuring the quality of the system-on-a-chip and expected to architect testbenches, define methodology, coverage plans, test plans, tests. You will work with design and micro-architecture teams to understand the functional and performance goals of the project. You will evaluate design specs as they are written, conduct verification plan reviews, develop block level tests and triage failures. Your diplomatic skills will be required to find collaborative approaches to resolve bugs you find while owning the verification efforts in your area of the design. You will also need to balance our team goals while coordinating engineering efforts across the diverse teams that use our hardware.

Education & Experience

BSEE or BSCS required, Master's or PhD desired.



Requirements

See job description

 

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