Spanish bilingual and Hispanic jobs since 1997. Diversity job fairs since 2006. employers     login   |   register - post a job
Hispanic Diversity Recruitment - best jobs for hispanic, latino & bilingual (spanish & portuguese) jobseekers
    Log me in!   |   Site Map   |   Help   
 RFIC Design Engineer - PLL - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Engineering - Telecom
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200204885 / Latpro-3760726 
Date posted: Nov-04-2020
State, Zip: California, 95014


RFIC Design Engineer - PLL

Santa Clara Valley (Cupertino) , California , United States



Posted: Nov 4, 2020

Weekly Hours: 40

Role Number: 200204885

Would you like to join Apple's fast-growing mmWave and cellular wireless design team? Do you love working on technical challenges no one has solved yet? We have an opportunity for a talented RF and PLL designer to open up the boundaries and craft novel techniques that overcome traditional circuit and architecture bottlenecks. In this role you will have the opportunity to do innovative development in PLL and transceiver design while working closely with systems and product teams at Apple. Come join us and make a critical impact on getting products to millions of customers!

Key Qualifications

  • Innovative and out of the box thinking to solve challenging and difficult problems.
  • Deep understanding of overall RF system and circuit level requirements.
  • Hands-on experience with PLL top-to-bottom level spice and mixed mode design and simulation.
  • Strong knowledge of RF architecture and blocks such as transceivers, VCOs, LNA and up/down converters. Good knowledge of ADC/DAC designs/architectures would be helpful too.
  • Experience in Matlab/VerilogA modeling and strong device physics knowledge as it applies to analog IC designs.
  • Working knowledge of bandgaps, bias, opamps, LDOs, feedback and compensations techniques is a bonus.
  • Bring-up and debugging skills, experience in working with production test engineers to create test plans and design for testability.


  • Design Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.
  • Conduct high speed digital circuit design and timing/phase noise analysis.
  • Create behavioral models of PLL to drive architectural decisions and derive block-level requirements for analog and digital blocks.
  • Work closely with mask design team to implement layout view of designs.
  • Construct lab and ATE test plans; take measurements/debug for characterization and volume production.

    Education & Experience

    MSEE with expertise in related areas is important to have; PhD preferred.

    Additional Requirements

    • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
    • We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

  • Requirements

    See job description


    Apple requires you to fill in their on-line form which will open in a different window.

    Enter your email address and click 'Apply':
      Prefer not to enter your email?