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 Cellular SoC Design Engineer - San Diego, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Engineering - Telecom
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200204949 / Latpro-3760793 
Date posted: Nov-05-2020
State, Zip: California, 92101

Description

Cellular SoC Design Engineer

San Diego , California , United States

Hardware

Summary

Posted: Nov 4, 2020

Role Number: 200204949

Join Apple's growing wireless silicon development. Apple's world class design and integration processes are driven by top notch integration engineers who own various blocks of the chip and coordinate with various teams to get all changes released to the database and production synthesized on the project scheduled delivery dates. This is a high visibility and mission critical role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design.

Key Qualifications

  • This position requires thorough knowledge of the ASIC design flow, FE and Design verification, synthesis, scripting and netlist generation. The ideal candidate will have the following background:
  • At least 10+ years experience in ASIC design flow
  • Proven track record of high performance designs in high volume production for low power applications
  • Proven track record of RTL design and timing closure on large complex designs
  • Expertise in:
  • SOC IP integration and RTL Design for performance, low area, and low power
  • FE production synthesis with DFT insertion
  • ASIC design flow and netlist flow checks - Lint, CDC, Logical Equivalence
  • UPF flow for defining power intent of chips with multiple power domains
  • Design interfacing to PD for floorplanning and timing closure
  • Strong communication skills are a must as the candidate will interface with a lot of different groups within and outside the company
  • Self starter, highly motivated, highly organized, and schedule driven is a must
  • Familiarity with DFT and backend related methodology and tools is a plus

Description

You will be responsible for the following: 1) Oversees definition, design, verification and development of SoC architecture. 2) Performs all aspect of SoC design flow from high-level design, RTL implementation, synthesis and physical design. Define chip level architecture, Perform logic design and system simulation. 3) Top level integration of connectivity, system bus, peripherals and CPU IP. 4) Works closely with physical design team to complete GDS. 5) Develop and maintain methodology/flow/checks for your design. 6) Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process

  • Core Responsibilities:

    Education & Experience

    BSEE is required. MSEE is preferred.



  • Requirements

    See job description

     

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