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 Senior Packaging Engineer, PPO-Sensing Group - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Engineering - Electrical
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200211110 / Latpro-3764934 
Date posted: Dec-10-2020
State, Zip: California, 95014


Senior Packaging Engineer, PPO-Sensing Group

Santa Clara Valley (Cupertino) , California , United States



Posted: Dec 9, 2020

Weekly Hours: 40

Role Number: 200211110

Apple's PPO Sensing Group is looking for a senior level electronic packaging engineer to work on developing exciting new products. Be responsible for providing module packaging solutions in a system for various consumer markets. Report directly to the Advanced Packaging Manager, working with internal device design, product design, operation, and supply chain; and also the external suppliers to develop and deploy new packaging technologies. We are looking for individuals who are very innovative with a proven track record to reduce to practice in a high volume manufacturing environment.

Key Qualifications

  • 10+ years of semiconductor packaging/assembly experience.
  • In-depth knowledge in the area of MEMS sensor packaging technologies, and MEMS chip-to-package interactions. Know how to leverage package knowledge to de-risk sensor performance degradations.
  • Familiar with assembly substrate design rules and package/module design rules and be smart about challenging design rules and advance design rules.
  • Expert level knowledge in assembly steps: wafer thinning, wafer dicing, die attach (including flip chip and multi-die stacking), wirebond, encapsulation and underfill, singulation and wafer level packaging processes.
  • Working level knowledge in wafer bumping, RDL, and TSV.
  • Strong materials science and engineering knowledge and failure analysis (FA) capability related to assembly chip-packaging interactions and reliability failures.
  • Proficient in applying DOE vs. Hypothesis tool for root cause analysis.
  • Be able to conduct independent research to understand the industry landscape on relevant technologies.
  • Knowledge of advanced packaging is a plus.
  • Strong interpersonal skills and open-minded to work with cross functional teams, and apply technical influences.
  • Excellent written and verbal communication skills.
  • Present ideas, design concepts, data and plan with high confidence at team meetings and executive review meetings.
  • Have passion in semiconductor packaging technology, self motivated, can go deep, and be able to deliver under minimal supervision.
  • Proven track record to work with OSAT to bring up a product from conceptual to MP stage.
  • Drive MEMS and sensors roadmap in optimized performance with package architecture, novel packaging materials, and system integration.
  • Previous knowledge in magnetometer (TMR/GMR/Hall Effect) packaging is a plus.


Define new package special characteristics based on unique system level performance, cost, and footprint requirements. Own package design function including conceptual and layout approval. Use FMEA to define risk items and mitigations. Use Major Issue List to initiate, track and direct OSAT's development activities. Develop a scale-able assembly process from design phase, which includes but not limited to, the initial proof of concept demo, novel process, equipment and materials development, process control plan, IQC and OQC, yield analysis and enhancement. Establish and transfer POR (process of record) to Operation Team on time before ramp-up. Interface and coordinate with other team members to meet product development/ramp schedule. Package/module signoff at various milestone stages. Define packaging roadmap based on long term packaged product requirements. Manage suppliers' R&D activities.

Education & Experience

M.S or Ph.D. in Mechanical Engineering, Physics, Materials Science or similar disciplines.


See job description


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