Sr. SerDes Circuit Design Engineer
Santa Clara Valley (Cupertino) , California , United States
Posted: Dec 16, 2020
Weekly Hours: 40
Role Number: 200211189
In this role, you will actively work within Analog-Mixed/Signal design team and participate in bring-up of embedded circuits; collaborating with many fields to enable the world's premiere products. You will closely work with a talented group of Analog-Mixed/Signal designers working diligently to deliver hard IPs to Apple's products while exceeding the highest expectations of quality, innovation and efficiency. At Apple, we work every single day to craft products that enrich people's lives. And in doing so face great challenges as SOC/PHY design complexity. If you have strong fundamentals and a track record of tackling technical challenges. If you are inspired by your curiosity and eagerness to learn new skills and to improve the value and impact of your work. If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems. If you love working with people and teams with multifaceted strengths to accomplish great things. We have an opportunity for a forward-thinking and especially hardworking analog mixed signal engineer with background in high speed serial links circuit blocks. As a member of our team with varied strengths, you will have the rare and great opportunity to work on upcoming products that will surprise and delight millions of Apple's customers! And all of this while enjoying a strong culture where you lead your career!
- The ideal candidate should have proven fundamentals in analog mixed-signal design with proven understanding and experience in high-speed serial links.
- Very knowledgeable about and experience with common high-speed SerDes protocols (e.g., PCIe, USB, SATA, etc.)
- Solid understanding designing AMS circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
- In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
- Strong understanding of Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE
- Experience with and knowledge of CDR architectures and implementations, e.g. PI based, PLL based, source-synchronous/clock-forward, ...
- Experience with ADC based SerDes and DSP requirements
- Knowledge of high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.)
- Experience in analyzing link jitter budget and modeling for high-speed serial links and creating block level requirements
- Design experience in advanced CMOS technologies, design with FinFet technology
- Experience in lab testing of high-speed serial links and resolving issues
- Experience in leading mixed-signal development teams from initial architectural definition, specification, circuit development, layout, tapeout, silicon bringup and production ramp
- EXPERIENCE IN THE FOLLOWING AREAS IS DESIRABLE:
- Static timing analysis tools (e.g., Nanotime, Primetime, etc.)
- Modeling of digitally assisted analog adaptive loops (using C, Matlab or Python, etc.)
- Able to build VerilogA/AMS behavioral models
- Able to analyze and lead characterization data from lab and volume testing
- Knowledge of ESD requirements
Ownership of SerDes PHY architecture and implementation, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, clock generation and distribution, etc.) Build block-level specifications based on link-budget, behavioral modeling and transistor-level feasibility, and drive design to completion Work with multi-functional teams to define requirements/specs (e.g., modeling, package, board, DFT, ESD, etc.) Drive mask design to implement layout view of designs Generation/QA of various IP Kit views/files for release to IP consumers Hold design reviews of blocks with peers/management to show design meets spec targets and requirements Defining production/bench-level test plans Drive silicon debug, bringup and production ramp Analyze and summarize production data and drive closure to design issue
Education & Experience
MSEE with 10+ years or PhD with 7+ years of proven experience. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.