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 Mixed-Signal Verification Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Other
Computers - Platforms
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200213602 / Latpro-3767301 
Date posted: Dec-29-2020
State, Zip: California, 95014

Description

Mixed-Signal Verification Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Dec 28, 2020

Role Number: 200213602

Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this role, you will be verifying RF/Mixed-Signal blocks and SOCs using SystemVerilog to create testbenches, checkers, models and tests. You will build and execute test plans to meet project schedule and metric requirements, including coverage metrics.

Key Qualifications

  • 3+ years of industry verification experience with RF/Mixed-Signal blocks and SOCs.
  • Expertise building Mixed-Signal testbenches, checkers and tests.
  • Expertise creating and using real-numbered analog behavioral models in SystemVerilog/Verilog-AMS or electrical behavioral models in Verilog-A
  • Experience in HVL methodology (UVM/OVM/VMM) and HDL (SystemVerilog, Verilog) for verification.
  • Strong verification skills in problem solving, constrained random testing, and debugging.
  • Understanding of common analog/RF blocks.
  • Experience with signal processing using Python or Matlab a plus.
  • Experience with Virtuoso Composer, ADE and HED a plus.
  • Team spirit, excellent communication skills and the desire to take on diverse challenges.

Description

  • Review specifications, extract features, define and execute verification plan.
  • Develop top/block level Mixed Signal and Digital testbench and generate directed/ constrained random tests in a UVM framework.
  • Build and reuse real numbered analog behavioral models, monitors, and checkers for RF/Mixed-Signal blocks.
  • Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage.
  • Write scripts for automation of flow.
  • Improve Mixed Signal verification methodology.

    Education & Experience

    BSEE is required, MSEE/PhD preferred.

    Additional Requirements

    • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.





  • Requirements

    See job description

     

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