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 PLL Design Engineer - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Software Engineer
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200201935 / Latpro-3768283 
Date posted: Jan-08-2021
State, Zip: California, 95014


PLL Design Engineer

Santa Clara Valley (Cupertino) , California , United States



Posted: Jan 7, 2021

Weekly Hours: 40

Role Number: 200201935

At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and especially talented PLL Designer. As a member of our multifaceted group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every day! Apple Silicon Engineering is seeking qualified PLL designers to work on the next generation PLLs for Apple's world-leading systems-on-chip (SOCs). You will be part of a growing analog/mixed-signal team involved in design and productization on leading-edge CMOS process technology nodes.

Key Qualifications

  • Understand system level requirements to create overall PLL specifications.
  • Create behavioral models of PLL to drive architectural decisions and derive block-level requirements for analog and digital blocks.
  • Work closely with mask design team to implement layout view of designs.
  • Complete top-level spice and mixed-mode simulations to validate top-level integration.
  • Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
  • Define production/bench-level test plans for post-silicon characterization.
  • Work with lab engineers in taking lab measurements to validate IP.
  • Review ATE and lab test results to resolve yield issues and drive bug fixes.
  • Work with system teams in system bringup and debug.
  • Hold design reviews of blocks with peers/management to show design meets spec targets and requirements.


The ideal candidate should have proven taking chips to production with experience in the following areas: Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs, Digital PLL techniques, etc. High speed digital circuit design and analysis (e.g., STA, formal verification). Digitally assisted analog circuit and techniques. Good knowledge of band gaps, bias, op-amps, LDOs, feedback and compensation techniques. Experience in VCO design including but not limited to LC VCOs. Lab and ATE test plans and measurement for characterization, and volume production.

Education & Experience

MSEE 3+ yrs in related area of expertise or PhD


See job description


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