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 Sr. Timing Engineer - San Diego, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Other
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200230405 / Latpro-3778382 
Date posted: Mar-12-2021
State, Zip: California, 92101


Sr. Timing Engineer

San Diego , California , United States



Posted: Mar 12, 2021

Role Number: 200230405

At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product.

Key Qualifications

  • At least 10+ years experience in ASIC design flow
  • Expertise in STA tools and flow.
  • UPF flow for power islands as well as voltage islands
  • Knowledge of timing corners/modes, process variations and signal integrity related issues.
  • Hands on experience in timing/SDC constraints generation and management.
  • Proficient in scripting languages (Tcl and Perl).
  • Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools.
  • Knowledge in logic optimization, synthesis, static timing analysis, floor-planning.
  • Fluent with RTL Verilog/VHDL
  • Familiarity with digital top integration flows/methodology/checks.
  • Experience with script-based tool automation and familiarity with API's and scripting languages for design tools such as Design Compiler, PrimeTime, etc... is a plus


- Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation). - Develop and maintain methodology and flows related to timing verification and closure. - Generation of block and full chip timing constraints. - Experience in low power design and implementation technique, knowledge of UPF and power intent verification. - Support digital chip integration work and flows. - Work closely with Chip Architecture, Design verification, Physical Design, DFT, and power teams to achieve first tape out success on designs. - Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process.

Education & Experience

MSEE or Equivalent required


See job description


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