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 Wireless SoC Design Integration Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Other
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200230414 / Latpro-3778383 
Date posted: Mar-12-2021
State, Zip: California, 95014

Description

Wireless SoC Design Integration Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Mar 12, 2021

Role Number: 200230414

At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product.

Key Qualifications

  • You bring at least 10+ years of experience.
  • This position requires detailed knowledge of the ASIC design flow.
  • Top level integration of connectivity, system bus, peripherals and CPU IP
  • Strong experience in complex ASIC design and IP integration, with focus on high performance, low area, and low power.
  • Successful tape outs of complex, high-volume SoCs in advanced design nodes.
  • Proficient in design methodologies and EDA tools for DFT, power, clocking and debug
  • Experience working with back-end tools including synthesis
  • Expert knowledge of ASIC design flow and netlist flow checks - Lint, CDC, Logical Equivalence.
  • Expert knowledge of UPF flow for defining power intent of chips with multiple power domains.
  • Understanding of multi-clock designs, power management, reset and power sequencing.

Description

- Responsible for chip level design infrastructure. - Evaluate standard hardware IPs for integration into new SoCs - Review architecture and design of custom IPs for integration into new SoCs - Design and develop interface logic and top level netlists for new SoCs - Develop and implement methodologies for I/O, DFT, debug, clocking and power - Responsibility includes feasibility, micro-architecture, RTL design, front-end implementation and post-silicon system bring-up. - Implementation and verification of design in RTL and taking the design through all the FE flows. - Ownership of the Integration Spec for the design project, integration and optimization of any memories and hard macros, - Provide technical leadership through personal example, mentorship, and strong teamwork

Education & Experience

MSEE or Ph.D. preferred



Requirements

See job description

 

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