Signal Integrity Engineer
Santa Clara Valley (Cupertino) , California , United States
Posted: Apr 2, 2021
Weekly Hours: 40
Role Number: 200235943
The candidate will work \within the Mac organization to support the system-level Signal Integrity (SI) and Power Integrity (PI) design, analysis and validation aspects of Mac and Accessory products development. You should have deep knowledge and familiarity with all aspects of Signal Integrity for high speed Serdes, parallel bus, single ended signaling, and signaling interfaces deployed in personal computers and peripherals well as power delivery network design, analysis and validation methods.
- The candidate must have a solid technical understanding of power supply architectures covering voltage regulator technologies, power distribution network (PDN) modeling, PCB design practices and trade-offs for PDN design and optimization.
- In particular, candidate is also required to have a good understanding of multi-phase of Buck/Boost converter and LDO design principles, operating modes, and system integration careabouts.
- The candidate must have system level Serdes design and analysis skills. The Serdes knowledge required includes understanding of transmitter and receiver equalization methods (including FFE, CTLE, DFE, VGA gain), CDR behaviors and modeling, and link training algorithms.
- Serial bus expertise shall include knowledge of the specifications of PCIe, USB3.1, DisplayPort, and Thunderbolt. SI skills required include DOE analysis across channel variants, applying equalization and training as required for end-end channel analysis.
- Parallel bus interface expertise should include understanding of signaling specs and signal integrity sign-off for DDR, GDDR, LPDDR, NAND interfaces, and common synchronous interfaces.
- The candidate should be able to model physical signaling channel topologies including differential, single ended, and parallel bus types. - Interconnect modeling capability, using S-parameter, W-elements, etc is required.An understanding of channel types including cabling, pcb materials, flex materials, and connector design methods and limitations is required. - Good working knowledge in 3D/2D EM simulation tools, electromagnetic modeling and transmission line theory is required. - Skills with associated tools for 2.5D (PowerSI, SIWave, Sentinel-PI, nSys), 3D Full wave (HFSS, nWave), quasi-static tools (Q3D, nApex)is required. - Relevant working knowledge of HSPICE, Spectre, AMS, and Simplis models for system-level transient analysis is also necessary. Working knowledge of ADS is desired. - Measurement expertise with frequency and time domain tools (VNA, TDR) including calibration methods is desired. - The candidate is expected to work with Silicon, System Architecture and System engineers to validate architectural implementation targets, and perform necessary pre-layout and post-layout analysis for guidance and convergence of SI and PI design solution space for target system implementation. - The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. - Ability to execute on channel analysis, target impedance analysis, transient voltage droop and phase margin/stability analysis is required. - The candidate is also expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase. - The candidates is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design SIPI margins. - Experience with PERL and other scripting languages is desired. MatLab Experience is a plus. - Excellent documentation and communication skills, ability to work independently, and demonstrated ability to innovate are required. - Candidate is also expected to have demonstrated experience in driving initiatives that improved process, procedures, and result quality.
Education & Experience
PhD (Preferred), or Masters (minimum) with at least 7-8 years of industry experience.