ASIC/FPGA Prototyping Design Engineer
Santa Clara Valley (Cupertino) , California , United States
Posted: Jun 3, 2021
Role Number: 200253296
Come join Apple's growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply.
- Typically requires proven experience with bring up, debugging and verification on FPGA
- Experience in FPGA development for wireless applications strongly preferred
- Proven understanding of wireless standards, such as IEEE 802.11, Bluetooth is a plus
- Experience with FPGA platforms: Dini, HAPS - including compilation, debug, performance and throughput tuning
- Experience writing 'make' based build system
- Experience with C++ and python highly desirable
- Maintain common design platform for ASIC as well as FPGA, with considerations for memories, I/O Pads, gated clocks and complex generated clocks.
- Design and verification using Verilog/System Verilog
- Perform FPGA Synthesis, Place & Route, timing optimizations
- Perform bring-up, debug, and validation of designs to achieve functional and performance goals
- Create and execute plans to bring-up, debug, and validate designs
- Thoroughly document and support each of above steps
- Collaborate with cross-functional teams in order to define prototype hardware to evaluate new technologies and features
- Creates emulation/Field Programmable Gate Array (FPGA) models from a register transfer level (RTL) design using emulation/FPGA synthesis, partitioning and routing tools - Develops hardware and software collaterals and integrates it with the emulation/FPGA model - Tests and debugs the emulation/FPGA model and collaterals - Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-silicon and post-silicon functional validation as well as software development/validation - Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform - Collaborate with and provides guidance to pre-silicon Validation teams for optimizing pre-silicon validation environments, test suites and methodologies for emulation efficiency - Develops and applies automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization - Front-end ASIC design experience - Micro-architecture and design of high-performance DMAs/data transfer engines/interconnects - Computer architecture, SoC fabrics/interconnects, memory controllers, arbitration, flow control, caching, etc - RTL design and verification - System Verilog, scripting and modeling languages (e.g. Python, Perl, C) Lint, formal equivalence - Verification test benches, coverage analysis, formal verification - Knowledge of bring-up and debug of FPGAs and silicon - Familiar with common on-chip bus protocols such as AMBA (AXI, AHB, APB) - Collaboration, schedule and resource planning, and task/team management skills
Education & Experience
MS in Electrical Engineering preferred.