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 Cellular SoC Integration Test Engineer - Cupertino, California, United States

Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Engineering - Telecom
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200268844 / Latpro-3808018 
Date posted: Jul-21-2021
State, Zip: California, 95014


Cellular SoC Integration Test Engineer

Santa Clara Valley (Cupertino) , California , United States



Posted: Jul 20, 2021

Role Number: 200268844

Are you a highly motivated self-starter with a passion for innovation? Do you thrive on pushing the limits of what's considered feasible? As part of our team, you'll create and deploy sophisticated design verification and emulation platforms to test the performance limits and root cause the reasons for those limits of state-of-art Cellular ICs. This is a high-visibility mission-critical role in the SoC design integration team and requires close working relationships with SoC design, design verification, silicon validation, and emulation engineers. By collaborating with other teams, you'll push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world.

Key Qualifications

  • 3+ years of hands-on SoC verification and/or verification on FPGA/emulation systems.
  • Knowledge of embedded CPU subsystems, and experience in writing and simulating C/C++ code on these CPUs.
  • Knowledge of SoC design elements: CPUs, bus fabric, peripherals, and power/clock microarchitecture, and debug capabilities.
  • Knowledge of SystemVerilog for RTL and testbench design.
  • Excellent communication and problem-solving skills.


  • Understand SoC architectures of complex chips with multiple CPUs, DDR memory interface, PCIe host interface, sophisticated bus fabric, host of peripherals such as SPI/I2C/UART/timers, and many other subsystems.
  • Understand the current design verification and silicon validation methodologies on coverage, performance, and power analysis.
  • Create & deploy test cases that exercise complex data/control interactions between SoC subsystems.
  • Create & deploy test cases that stress the SoC and measure E2E performance under diverse traffic conditions.
  • Create multi-chip DV environments and tests to support multi-chip pre-Si HW platform design/bring-up/debug.
  • Develop a comprehensive system debug methodology for triage & debug of pre-Si HW platform bring-up issues.

    Education & Experience

    BSEE or equivalent required. MSEE is preferred.

  • Requirements

    See job description


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