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 CPU Power RTL Micro-architect - Beaverton, Oregon, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Platforms
Computers - Networks
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200286533 / Latpro-3822638 
Date posted: Sep-10-2021
State, Zip: Oregon, 97005

Description

CPU Power RTL Micro-architect

Beaverton , Oregon , United States

Hardware

Summary

Posted: Sep 9, 2021

Role Number: 200286533

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products! We are looking for an experienced technical leader to guide and direct world-class CPU power and clock management solutions.

Key Qualifications

  • Microarchitecture development and specification - from early high-level architectural exploration through microarchitectural research and arriving at a detailed specification
  • RTL ownership - development, assessment, and refinement of RTL design to target power, performance, area and timing goals
  • Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power
  • Knowledge of Verilog and/or VHDL
  • Experience with simulators and waveform debugging tools

Description

As a member of the RTL and architecture team, the responsibilities would be in the refinement of solutions in the following areas:

  • Dynamic voltage and frequency scaling (DVFS/DVFM)
  • Power state definition and management
  • Dynamic clocking solutions
  • Micro-architecture strategies for improved power integrity
  • Debug solutions
  • Error handling
  • Reset control
  • Clock generation and asynchronous clock crossing strategies

    Education & Experience

    Bachelor's in Electrical or Computer Engineering is required. Master's or PhD in Electrical or Computer Engineering is preferred.



  • Requirements

    See job description

     

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