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 CAD Timing Engineer - Cupertino, California, United States

   
Job information
Posted by: Apple 
Hiring entity type: Retail 
Work authorization: Not Specified for United States
Position type: Direct Hire, Full-Time 
Compensation: ******
Benefits: See below
Relocation: Not specified 
Position functions: Computers - Programming Languages
Computers - Platforms
Computers - Networks
Computers - Software Engineer
 
Travel: Unspecified 
Accept candidates: from anywhere 
Languages: English - Fluent
 
Minimum education: See below 
Minimum years experience: See below 
Resumes accepted in: English
Cover letter: No cover letter requested
Job code: 200287246 / Latpro-3823251 
Date posted: Sep-12-2021
State, Zip: California, 95014

Description

CAD Timing Engineer

Santa Clara Valley (Cupertino) , California , United States

Hardware

Summary

Posted: Sep 10, 2021

Role Number: 200287246

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor and system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. We invite you to help deliver the next groundbreaking Apple products. In this highly visible role as a key technical member of the Design Methodology and Tools team, you will be an integral part of the effort to improve the performance of Apple silicon. You will be responsible for delivering industry-leading solutions for design optimization, design closure, and visualization. Combining algorithm application with practical design know-how and software engineering best practices, you will help to differentiate and streamline Apple's silicon engineering methods.

Key Qualifications

  • Typically requires 5+ years of hands on experience in static timing analysis and/or design optimization flows
  • Familiar with STA of large high-performance SoC or Processor designs in deep sub-micron technologies
  • Strong analytical skills and ability to identify high ROI opportunities
  • Proven software engineering background and experience with C++, Python, Tcl programming languages
  • Proficiency with optimization algorithms, data modeling, and mathematical representations
  • Solid understanding of cross-talk, variation, and margining
  • Good communicator who can accurately assess, describe issues to management and follow solutions through to completion
  • Familiarity with timing and power ECO techniques and implementation is a plus

Description

As a CAD Timing Engineer, you will: - Deliver methodology and tool solutions for static timing closure and power optimization - Apply data science and ML analytics to quantify, mine, and predict intriguing patterns - Deploy innovative modeling and optimization approaches to achieve globally optimal targets - Prudently apply best-in-class algorithms and ECO techniques for value-adding design solutions - Pursue deep analysis of timing paths and power inefficiencies to isolate key issues - Implement code infrastructure to facilitate analytics and visualization - Collaborate with silicon design, CAD, and EDA partners to identify flow deficiencies and enact creative remedies

Education & Experience

BS, MS/PhD* preferred, degree in technical field (*if fewer years of experience)



Requirements

See job description

 

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